https://dl.dropboxusercontent.com/s/uke8194tracc1mj/macronix_sgvc_3d_nand_lue2017.pdf
The specs they listed include the "CMOS peripheral" specific to the test chip they manufactured, so not the interface of a Switch game card.
Thanks. One thing I find funny is that the paragraph about it being suitable for "game-grade memory" is bolded, and is the only bold text in the paper. Of course it's also the least technical paragraph, so presumably they just want to highlight potential uses to anyone who doesn't understand the technical details. The line after it is also relevant: "Without the need to refresh and wear leveling, it is very advantageous for system design." I'm curious if they have to perform cell refreshing at all in NAND-based Switch game cards. Even without writing to the cards, read disturbance could mean refreshing is required, which would add complexity and cost which this would remove.
The P/E (program erase) cycle count is relatively low for MLC NAND at about 1K. I believe MLC NAND is typically around 10K, with 1K P/E cycles being more typical for QLC. Given the claimed high density and low cost of SGCV NAND, though, they would probably be competing more with QLC NAND anyway. Not too relevant for Nintendo in an OTP ROM use-case, but interesting to see the trade-offs.
The CMOS peripheral area is, as I understand it, for basically everything but the NAND cells themselves, eg page buffers, the physical I/O circuits, etc. You can see it at the bottom of the photo of the chip. They state they plan to switch to CMOS under array (CuA), which would move it under the NAND circuits, which saves space and allows for higher NAND density for a give chip size. There's a short explanation of it on pages 10 and 11 of
this paper. In this particular case it's a standard NAND interface (probably ONFI), but I wonder how flexible the manufacturing process is here. Could they implement a custom Nintendo interface and security hardware on there? Could they license IP for a high speed interconnect like PCIe or M-PHY and fabricate it directly on the CMOS part of the chip? If so it would presumably bring down costs quite a bit than requiring a separate I/O / security die.
I went digging and not shockingly came back to this thread. . .
Now this isn't the chip between the Game Card interface and Switch motherboard, but the customization for Drake could imply additional Nintendo specific features.
One thing that's worth noting is that all Switch data is encrypted, regardless of whether it's on a game card, internal storage or removable storage, so they need on-chip decryption capabilities regardless. I believe the game cards have a few extra security checks to make sure it's a genuine game card, but for general decryption duties they still need to be able to work with encrypted eMMC/SD data. For Switch NG ideally they pipe this directly into the file decompression engine, so data can go directly from storage to decryption to decompression to RAM without unnecessary copies.
Last I saw, Nintendo has a M-PHY license already, even though there's nothing to indicate they've yet used it in shipped hardware. That may just relate to eUFS (or even UFS Card for external storage), but if it serves the purpose and they're already working with it... why not, right?
They've been an adopter member of the MIPI alliance
since 2013, it seems, which gives them licenses to all of their specifications. I think they're using DSI for the screen in the Switch, which is a MIPI spec, which is presumably why they joined, but it does mean they have an M-PHY license. They're also
a member of the PCI SIG, though, which means they have a license for PCIe too. Membership of these groups is only a few thousand dollars a year, so pretty much pittance for a company like Nintendo.
www.engadget.com
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