So, doing a bit of a search around on LLW RAM, there are a few tidbits (in the midst of baseless speculation that it'll be used in the Galaxy S24). Here's a video posted by Samsung on Twitter, showing a few things:
This first thing to note is that it's on-package alongside the SoC, which would appear to confirm my suspicion that it's based on HBM. You can also see it inside a variety of vague CG renders of a phone, laptop and a gaming controller (yes, a controller). A couple of the examples show it alongside regular DRAM, which is a little surprising, but I suppose it could be used kind of like the bizarre Intel/AMD hybrid Kaby Lake G, which included an AMD GPU with HBM on-package, but still had regular DDR for the CPU.
The other thing I noticed, which is getting pretty technical and is probably just spurious speculation, but at 11 seconds you'll see a diagram of the memory, with multiple different banks transferring data seemingly independently. The curious part of this is that this doesn't actually represent how HBM memory works. Data accesses instead get routed to a central stripe, which then routes it down through the TSVs to the I/O (see figure 2 in
the Nvidia paper I linked). Why is this interesting? Well, that Nvidia paper proposes a new type of RAM based on HBM called Fine-Grained DRAM, or FGDRAM. The point of FGDRAM is precisely to change this paradigm of data access to save power and (in some cases) improve performance.
Not only does the diagram of LLW RAM look a lot more like FGDRAM than HBM (see figure 5 in the paper), but LLW seems to have a very similar design goal in reducing power consumption. It does make me wonder if LLW RAM is, if not actually FGDRAM, inspired by it. There are some differences, as FGDRAM has higher hardware latencies than HBM (although the paper claims that the architecture reduces queuing delay to the point where effective latency is lower), whereas LLW is claimed to be a low-latency RAM.
Speaking of which, there is a specific claim on latency
here, where they state tRCW < 32ns. The tRCW metric isn't one I've come across before, but from
this paper, it appears to be Write Row Cycle Time, where tRCW = tRP + tRASW, or the row recharge time plus the write row active time. I can find tRP figures for standard memory types like DDR5, but tRASW doesn't really seem to be something that I can find hard numbers for, so I can't really say how good a tRCW figure of < 32ns is.