Thanks, unfortunately the link does work for me (I'm getting a "sci-hub.se cannot be reached" error).
The specs are interesting, but there's probably not a whole lot to read into them. 3.3V/1.8V are standard for NAND chips (although 1.2V is becoming more common now). The interface, if it's a standard x8 configuration, would give 133MB/s, but (a) this was six years ago, (b) given it's a test chip to prove out the technology, the interface may not have any relationship to what they'd use on final hardware, and (c) if they used this on a game card they probably wouldn't use a standard flash interface anyway. The 48TSOP package seems to be commonly used on a variety of Macronix parts. I think they only use 16LGA on Nintendo game cards currently, but it is a reasonably common standard used by other manufacturers.
It's hard to say. They were getting 133MB/s on test chips in 2017 (with all the caveats listed above), so it's probably a reasonably safe assumption that they could hit higher speeds on production chips in 2024, but any number we could come up with would be purely a guess.
I suspect the bigger issue might be the interface between game cards and the console. They currently use an 8-bit wide SPI-style interface, clocked at either 25MHz or 50MHz, providing up to 50MB/s of bandwidth. It's an evolution of the interface they've used going back to the DS, and although it has the benefit of being simple and cheap to implement, it's not something you'd use to hit GB/s speeds. Macronix also use SPI-style interfaces for their serial NAND and NOR products, and the fastest parts they're offering run at 166MHz, with
a 200MHz part under development. I haven't found SPI interfaces in use much higher than 200MHz elsewhere, either, although I'll admit I haven't done a particularly thorough search. If Nintendo updated the existing game card interface to run at 200MHz, they'd get 200MB/s, which would be a decent upgrade on the current cards, although still well short of their internal storage (if they actually do use 512GB of internal storage, the slowest 512GB parts hit 1.7GB/s, and even 128GB/256GB UFS 2 would hit a baseline of 850MB/s).
So, if they want game cards much faster than 200MB/s, then they'll need to change the game card interface. Designing a gigabit-level interface from scratch in-house doesn't seem like a sensible use of R&D spending, so they would have to look for an existing standard they can use and potentially modify, and in particularly one which doesn't have per-device license fees. The only two I'm aware of that would suit their needs would be PCIe and M-PHY (the physical interface used by UFS). Both only require a small annual membership fee to the standards organisation and have no further license fees, and both match or exceed Nintendo's required performance and are widely adopted. They'll also continue to be improved with updated specifications for a long time.
If I were to guess, I'd say PCIe is more likely. It's more widely used, and T239 has ample PCIe connectivity. Even a single PCIe 4 lane (4 wires) would give them 2GB/s to work with. It would also allow them to connect the card slot directly to the SoC without any intermediate chips. Because the current Switch card interface is proprietary, it requires a separate chip on the motherboard which translates from eMMC commands from the TX1, and also provides a variety of crypto functionality. If they can move that crypto work onto the SoC, they can eliminate an extra custom IC and save costs.
