I hope nobody minds if I go on an absurd flight-of-fancy about something that's extremely unlikely, but it's been on my list of out-there hypotheticals for
literally years, so I felt like I had to go through the process on it.
Does Switch 2 use Samsung's new LLW DRAM memory?
(Spoiler:
Betteridge's law applies here)
Samsung
just announced a new type of memory called Low-Latency Wide I/O DRAM, or LLW DRAM. It's aimed at portable use-cases, offers high bandwidth (128GB/s per chip) and very low power draw.
From what I can tell, it appears to be similar to HBM,
which is backed up by their promo material.
The reason I find this so interesting is that I've been saying for years (see
here,
here, etc.) that a low-power RAM based on HBM would be the ideal, and possibly inevitable, solution for portable gaming devices like the Switch going forward. And here, right at the start of the year of Switch 2, Samsung goes ahead and announces a low-power RAM based on HBM with gaming as the only non-mandatory-AI-buzzword use-case tagged on their tweet.
Firstly, I'd like to go through
why HBM-style memory is so useful for a device like the Switch, as briefly as I can (which, let's be honest, usually isn't very brief!). The big issue here is that a portable gaming device like the Switch is always going to be limited by power consumption. There's going to be a maximum size battery they can fit in the device, and a maximum power draw they can sustain while getting decent life out of that battery. Improvements in battery technology are pretty slow, so improvements in performance from generation to generation are mostly going to come from getting more out of that limited power draw, ie improvements in power efficiency.
On the RAM side of things, this presents an issue, because the demand for bandwidth is growing at a greater rate than the power efficiency of that bandwidth. So, for the jump from Switch to Switch 2, we're looking at moving from 25.6GB/s of bandwidth to an expected 102.4GB/s of bandwidth, which is a 4x increase. However, from what I can tell power efficiency of LPDDR ram has only increased by around 2x over that time. So, if Nintendo want 4x the bandwidth, but only have 2x the efficiency, they need to allocate twice as much power to RAM to keep up. On Switch 2 they can likely just about do so, but at some point something's got to give, and they'll need an alternative to LPDDR.
This is where HBM-style memory comes in. HBM is stacked RAM which sits on an interposer next to the GPU/SoC. This gives it two big advantages in terms of power efficiency. The first is that it's a wide and slow standard. Instead of 16 to 64 bit interfaces, HBM modules have 1024-bit interfaces, which would be impractical to implement as traces over a motherboard, but is easily done on an interposer. The second is that, as the connection between memory controller and memory is only over an interposer, not motherboard traces, the connection itself consumes less power. Actual HBM used on products like Hopper still consumes quite a bit of power, but that's at high clocks, delivering massive amounts of bandwidth, and a scaled down "low-power HBM" version designed for mobile devices should manage to beat out LPDDR on both bandwidth and power efficiency by good margins. The downside, of course, being cost, which will be higher by virtue of both the stacked RAM and the need for packaging alongside the SoC on an interposer.
Samsung's LLW DRAM appears to be pretty much exactly the kind of low-power HBM that I was expecting, and it's also almost suspiciously well-suited to Switch 2. It offers 128GB/s of bandwidth, which is higher than the 102GB/s we were expecting, but not by a crazy amount, and at 1.2 pJ/b of claimed power consumption, at peak bandwidth that would come to only 1.2W. For reference, from what I can tell the LPDDR4 in the original Switch consumed about 1.5W for 25.6GB/s, and I've been expecting about 3W for RAM in docked mode on Switch 2 for 102GB/s, so coming in under Switch's LPDDR4 in power while offering 5x the performance would be pretty damn nice. It's in an almost perfect sweet spot for Switch 2's performance and power envelope.
It also
might be based on a Nvidia proposal for a low-power variant of HBM, or I might be reaching way too far with my analysis there, but two years ago when I was writing about this, I
speculated about Samsung and Nvidia partnering on a low-power HBM-based memory for a future Switch, based on Nvidia's FGDRAM, and LLW DRAM is eerily close to that. I was off by a little bit on power efficiency (1.5 pJ/b vs 1.2 pJ/b), and expected slightly higher total power consumption and bandwidth, but the actual part Samsung have produced seems a better fit for Switch 2 than my speculation (which would have been overkill on bandwidth).
Does the evidence we have for Switch 2 fit LLW DRAM?
Maybe if you want to really stretch things, but not really.
Our first evidence of the memory interface on T239 came from the Nvidia hack, where
T239 was listed as having 1 framebuffer partition (ie memory controller), compared to 2 on T234 (Orin). Orin has a 256-bit LPDDR5 memory interface, split into two 128-bit memory controllers, so if T239 has one memory controller, it stands to reason that it has a 128-bit LPDDR5 memory interface.
To play devil's advocate here, LLW DRAM would also very likely involve one memory controller. On Nvidia's HPC GPUs that use HBM, like Hopper, they use two memory controllers per 1024-bit HBM module, with a 512-bit interface per memory controller. As LLW DRAM will have a narrower interface than HBM, likely either 256-bit or 512-bit, it seems reasonable to expect Nvidia would use a single memory controller per chip.
However, what's not that reasonable is to expect this vastly different RAM type to Orin's LPDDR5 seemingly show up nowhere in the hack. It reportedly states that
LPDDR5 is used on "T23X and later", and it would be very weird for T239 not to count as "T23X and later". It would be doubly weird for a brand new and completely unique memory type (which would be arguably the most unique feature of the chip) not to get a mention anywhere.
Another piece of evidence we have on T239's memory interface is
this Nvidia Linux commit from December 2021. This states that "T239 has 8 number of mc channels while orin has 16 number of mc channels". That is, half as many memory controller channels as Orin, therefore reinforcing the info from the hack, that's it's a 128-bit LPDDR5 memory interface. Strictly speaking, this commit relates to pre-silicon testing, and is actually referring to LPDDR4, rather than LPDDR5, presumably for testing sake. Of course it makes sense to do pre-silicon testing with a very similar memory type like LPDDR4. It doesn't make a whole lot of sense to do that if the chip you're testing uses a memory that's nothing like LPDDR4. This file doesn't seem to still exist in Nvidia's public repos (or it's been moved somewhere I can't find), so I don't know if it's been updated to LPDDR5 since silicon hit.
Edit: And for one extra nail in the coffin while I was typing this up,
@karmitt's post on the last page seems to be extremely clear on LPDDR5/X.
So, LLW DRAM is almost certainly not being used in Switch 2, and that's kind of a shame. Not because it would allow for a big jump in performance, as it would actually come in at lower bandwidth than LPDDR5X, which is both more plausible and cheaper (although the lower power consumption may allow for a bit more power to be diverted to other components like CPU and GPU in portable mode). The real reason it's a shame is that it's exactly the kind of weird, unique technology we used to get in consoles back in the day, like when Sony would design an entire new CPU architecture from scratch for the PS3, or Nintendo would use some obscure memory tech, like in most of their hardware before the Switch. We don't really get that much any more.
That's not a bad thing overall, as designing completely new CPUs, GPUs or memory standards is way too expensive to do for a gaming console, and there are too many great options available off the shelf to go full Ken Kutaragi on a console, but as console hardware has become more standardised, it's become safer, and more predictable, and a bit more boring. The PS5 and XBSS/X were pretty predictable pieces of hardware all-in-all, with standard AMD CPUs and GPUs, standard GDDR memory, and relatively standard SSDs. The precise amount of GPU performance, or RAM or SSD bandwidth was up for debate, but the general architectures involved were never going to be surprising. The PS6 and next Xbox will almost certainly be the same, with standard AMD architectures and GDDR RAM wrapped up in the usual buzz-words that make it sound more custom than it is.
The Switch 2 is also looking remarkably sensible. After the shock on the GPU size when we learnt it from the hack, when you think about it as a 4N SoC, and with 4N being a pretty sensible choice in 2024, it's really quite a reasonable design. CPU and GPU architectures that are not quite the newest, but with very close performance, a CPU that aligns more closely to other consoles (8 cores) and a GPU that fits well within a small SoC, and can achieve high performance-per-Watt at Nintendo's target power levels. And then an LPDDR5 memory interface that provides bandwidth that's well-matched to the GPU's performance. The FDE is the one unique component, but as both Sony and MS had adopted dedicated decompression hardware it was hardly surprising.
A sensibly designed Switch 2 is the best case for people looking for a capable, reasonably priced piece of hardware, but a part of me wishes they would have gone a little crazy and used LLW RAM (although it was almost certainly developed too late to be an option). Just for a bit of the old mystery you used to get with gaming hardware, like trying to figure out what the hell 1T-SRAM was when Gamecube was announced. I'd say LLW RAM, or LLW2 or whatever becomes of it, is a pretty decent bet for whatever comes after Switch 2, but by that time it'll be the sensible choice, not the unique weird tech it would have been if it were used in Switch 2.