That's really interesting, I hadn't heard of nano imprint lithography before. It seems like it removes a lot of the complexity of photolithography, while undoubtedly adding a lot of complexity of its own.
From a brief read up on the tech (eg
here), it seems that the main challenge of the technology is alignment between layers. In the press release, Canon claims that its environment control technology "enables high-precision alignment", so perhaps they've made meaningful progress there. According to
this piece on Canon's website, they've had machines installed in one of Toshiba (now Kioxia)'s NAND fabs since 2017 for testing, and the first article claims they've also got hardware in use by SK Hynix, with plans to have NAND produced using NIL by 2025. The extremely high layer count of NAND means that alignment can't be terrible, although the larger feature size than bleeding-edge logic nodes probably gives it a bit more wiggle room than, say a 5nm class process would need.
There are a couple of other interesting differences to the technology compared to photolithography. One is that the feature size seems to be limited more by the mask than the actual lithography hardware. On a photolithography machine like ASML's EUV machines, there's a fundamental limit to the precision of that the machine can produce based on the physics of light at the wavelength used (hence the need to move from DUV to UEV to High-HA EUV).
With nanoimprint lithography, though, it seems as if the limit is the masks. In the press release, Canon state "with further improvement of mask technology, NIL is expected to enable circuit patterning with a minimum linewidth of 10 nm, which corresponds to 2-nm-node", meaning they could potentially see improvements in precision just from mask manufacturing without actually changing the lithography hardware. I assume there are practical limits to this, in terms of alignment and defect control, but unlike photolithography there doesn't seem to be a physical limit you're pushing against.
Another interesting difference is in mask sizes and the corresponding impact on chip sizes. On current photolithographic manufacturing processes, the size of the photomask, combined with the optics which reduce it onto the wafer, result in a maximum die size of around 850mm² (also known as the reticle limit). This is why huge HPC GPUs like Hopper are often around the 800mm² mark, as it's literally as big as they can make a single chip.
Based on
the specifications of the Canon NIL machine, the mask size is 6". I assume this is a 6" diameter circular mask, although in theory I suppose with there being no optical component to the lithography it could be any shape. Still, as NIL imprints directly from the mask to the wafer, the "reticle size" on Canon's NIL hardware is absolutely enormous. By my calculations, for a square die inside a 6" diameter circular mask, the maximum size would come to about 11,600mm². That's just under 11cm on each edge. The reticle limit on photolithography is becoming less of an issue with the move to chiplet architectures, and outside of Cerebras there isn't much demand for chips the size of coasters, but it likely contributes to the increased speed (and therefore reduced cost) of NIL compared to photolithography.
For modern photolithography, the process of manufacturing a layer on a full wafer consists of stepping the reticle across the wafer, exposing up to ~850mm² at a time. For Hopper, the reticle is the full chip, but for smaller dies like phone SoCs (or T239) the reticle could contain perhaps 8 or ten copies of the chip. To cover the entire wafer, the reticle might need to step to up to 100 different positions on the wafer, repeating the same lithography step each time.
With direct contact from a 6" circular mask, Canon's nanoimprint lithography machine could cover an entire wafer in just 9 steps. If it's a 6" square mask, that could cut that down to 4 steps. Even if each step is slower, it's easy to see how the entire process could end up much faster, and therefore cheaper.
Of course, this isn't really relevant for Switch 2 in any way, but it's very interesting to see some new underlying technology in this area, and it's not impossible that it could be used for manufacturing components in Switch 3, even if it's just the NAND.