Thraktor
"[✄]. [✄]. [✄]. [✄]." -Microsoft
- Pronouns
- He/Him
As per the announcement of the A78C it could be that the A78C is "DSU-100" and a special in-between variant to allow more A-cores into a cluster, thus creating a specific product -> A78C. The A78C documentation also just refers to the DSU . And the blog refers to an updated DynamicIQ unit.
I believe Thraktor essentially confirmed that in the past? Or perhaps was just similarly speculating.
The A78C is designed to be used with the DSU-MP135. You can see the phrase "For more information, see the Arm DynamIQ Shared Unit MP135 Technical Reference Manual." used whenever the DSU comes up in the A78C documentation, and in the X1C documentation, which also is designed for the DSU-MP135.
ARM reference cores can get a bit confusing, as a lot of the "features" of the A78C and X1C aren't actually features of the cores themselves, they're features of the DSU. In particular, the ability to use 8 A78C cores in a cluster is, strictly speaking, a feature of the DSU-MP135, not the A78C. Same with the larger cache, where the ability to use up to 8MB L3 is an implementation option of the DSU-MP135, not a feature of the core. It's also worth noting that the amount of L3 cache (or even the choice of using L3 cache at all) is independent of the number of cores. You can have a single A78C core in a DSU-MP135 cluster with 8MB of L3, and you can have eight A78C cores with 512KB of L3 cache, or even no L3 at all if you really want to live on the edge.
A final thing worth noting is that Nvidia don't have to use ARM's DSU cluster IP, they can take the cores and design their own cluster. They did this on the TX1 and TX2 and they used a custom cluster with custom cores on Xavier. It seems like both Orin and Grace use ARM DSU and interconnect IP (or something very similar to it), so my guess is they're doing the same on T239, but there's no rule that they have to. They could get a cluster with any number of cores and any amount of cache they want, they just have to design it themselves.