The leak I've seen is related to a Windows based NVN implementation for a dev kit. I imagine it has defines built around the hardware in a dev kit rather than the exact power of the device itself. I'm tempted to not read too much into it, but I am very dumb?
Well, I can tell you the other Ampere chips (and an Ada chip) are stated as 64 warps per SM, except for GA10X (sm_86) series which also says 48.
A few things: (1) A dev kit for Switch isn't Windows, it's modified Switch hardware, (2) this source code could build either the Windows reference implementation, which is meant for development -- though not for a dev kit -- or it could build for the real NX hardware, (3) anywhere the source refers to a Tegra chip like GA10F/T239, that's concrete in terms of what chip they're talking about and it can only be relevant to the NX hardware since Windows PCs don't have Tegras in them.
I don't think devkits typically use bigger/more performant GPUs than the target hardware has.
maybe?
Okay, so there's probably something more complicated going on here, as I think Ampere is supposed to be 128 CUDA cores per SM. I assume by GA10X you're referring to the desktop Ampere chips? If that's the case, then the numbers would line up, and would imply that this is just some funky architectural detail and it's still 128.
Ampere and Maxwell contain 128 CC per sm
I believe that in the devkits the GPU, CPU are clocked higher and more RAM are available for debugging purposes
FAMILY_GA10X or sm_86 is what they're defined as. According to this list, sm_86 appears to cover the desktop Ampere chips.
Ah do they?
True but the point still stands. They'll have the same GPU, physically speaking.I believe that in the devkits the GPU, CPU and more RAM are available for debugging purposes
So in a way they would be more performant
Okay, yeah, definitely sounds like the number probably isn't directly the CUDA core count, then, even if it might work out that way for TX1. This could imply that the chip is configured closer to the desktop cards than Orin, but I feel the need to emphasize that I really don't have an especially solid handle on what this number means.
There is in fact a lot of code that's only for the Windows impl to manage which Turing/Ampere GPU it's on and try to make it work properly. That's a big part of what makes it difficult to decipher what's really relevant for the Switch. On the subject of dev kits, GA10F is definitely the "main" Tegra chip NVN2 is meant to run on, but there are places that check for GA10B (Orin), so it's entirely possible that chip or some version of it was used in dev kits.
Well, can't really argue with the fucking source code.
Yeah Drake being stationary is something I thought about...
What are you guys talking about? This new system might not be hybrid?
yeah, and we have to consider that Orin is likely as big as it is primarily due to the A78AEs, DLAs, and other Automotive/AI stuff in it.
12SMs is stated in NVN2's Source Code which is way bigger of a GPU than any of us were really expecting.
There's no real indication that it won't be a hybrid, but there's new info now suggesting it will have a much bigger SoC die than we previously thought.
I haven't seen anything like that in either NVN1 or 2, although I can't claim to have a remotely thorough view of their contents. But I'd hazard a guess that things like docking and performance profiles are in the Nintendo SDK side of NVN, not the Nvidia graphics driver side.
Yeah, I imagine NVN probably wouldn't deal with this super explicitly. That stuff is probably mainly happening at abstraction levels both above and below what NVN deals with.
TL;DR, Hackers released DLSS's Source Code.
I don't think this is accidental, since the hackers are trying to illegally blackmail Nvidia in an attempt to force Nvidia to be open source. Damaging Nvidia's relationship with Nintendo to an extent is one way to do so.
And that's way bigger than expected, right?
So cool
I'm hoping Nintendo doesn't look down on Nvidia for this leak the way it's been said they looked down on Netflix for leaking the Zelda talks. I'm sure Nintendo can't just pull the plug on the Nvidia hardware relationship the way they pulled the plug on Netflix.
Yes. Personally I was expecting 4SMs and thought 8 was like the max possible, and extremely unlikely.
Okay I'm super ignorant so forgive me if this is off base but: would a configuration that runs at lower clock speeds perhaps help with backward compatibility? I remember people talking about concerns that games programmed for TX1 might not play nice with a much faster chip, so could "bigger, but still clocked low" possibly alleviate that?
I assume you're aware it stands for texture processing cluster. The extent of my knowledge is that GPCs contain TPCs which contain SMs. And actually, since the Ampere architecture evidently has two SMs per TPC, that would make the math check out with the 12 SMs as GA10F has 6 TPCs.
I don't think so because the GPU configuration will still be very different. I think either way they will need a software compatibility layer.
It means the power ceiling on this thing just jumped way up. Like, it could do 3-4TFlops before DLSS at high enough clocks.… Which is good, right?
Ah okay so it is 12SMs for Drake (1536 CUDA Cores, 6 RT Cores, 44 Tensor Cores?) just you have the FP32 FLOPs number (however NVIDIA defines it) for GA10B and GA10F.
I wouldn't really expect any BC benefits. Would probably mainly be a play for lower power consumption.
