HankyPanky
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well the device is larger so will house a larger maybe even significantly larger battery.Perhaps, but the clock speeds would have to be about 35% higher to offset the reduced core count. Again, my theory would assume that portable clock speeds would be right at 8nm Ampere peak efficiency, roughly 550-650Mhz I believe? Because an 8sm chip would have to be clocked 35% higher just to reach the same performance, it will operate in a less efficient parts of the power draw curve. What is the power draw for a 12sm chip at 650 Mhz compared to 8sm's at 1Ghz? Even worse on the bell curve would be docked power draw where the 12sm chip could be clocked at 1.1Ghz vs a 8sm chip at 1.6Ghz. The 8sm chip might actually draw more power at those clock speeds compared to the 12sm chip at the lower speed.
This is obviously just spit balling ideas and it of course is 8sm 8nm vs 12sm 8nm. There is no argument to me made against 4N in terms of performance or efficiency. Just looking 8nm and how a 8sm design might compare to a 12sm design. Once we remove the power budget limitations of the Switch and instead increase the power budget to match the efficiency sweet spot for 8nm, then things can start to make sense. As long as we are under the impression that the TDP for the SOC cannot be higher than 5w, it makes it impossible to square that with 8nm, but if that power budget is now 8-10 watts for portable mode and 15-20 watts for docked, suddenly 8nm is plausible again.
Not advocating for 8nm, still hoping its 4N, but if it does end up being 8nm, perhaps a higher power draw was an accepted part of the design from the get go.
again i'm not saying 8nm but there's enough things that point to it being possible.