There doesn't seem to be any information on the layer count, density, or capacity of anything Macronix is making, but
this TechInsights article from January has the specs for other manufacturers. Looks like 128 GB was the highest capacity being manufactured at that time, using 232 layers. All four listed manufacturers have 64 GB chips using 128 layers, and three of them have chips with more than 128 layers but still 64 GB capacity, which would decrease die size and cost.
The density at 128 layers ranges from 6.96 to 8.47 Gb/mm² (average 7.83), and from 10.27 to 11.01 Gb/mm² at 176 layers (average 10.72). The 232-layer chip has a density of 15.03 Gb/mm². This probably isn't a very sound extrapolation (assumes linear scaling, which is wrong), but the first two averages imply a factor of about 0.061 between the layer count and the density, so if we apply that to Macronix's apparent 3D NAND offerings, that would be 2.93 Gb/mm² for 48 layers, 5.86 Gb/mm² for 96 layers, and 11.71 Gb/mm² for 192 layers (or 12.7 Gb/mm² if we extrapolate from the 232-layer chip).
Macronix's SGVC paper from 2017 provided a chart of estimated (or confirmed in the case of 16 layers) densities, which I transcribe as follows:
Layers | MLC Density (Gb/mm²) | TLC Density (Gb/mm²) |
---|
16 | 1.6 | 2.4 |
24 | 2.5 | 3.3 |
32 | 3.1 | 4.2 |
48 | 4.6 | 6.2 |
Although we know the scaling isn't linear, I will note that MLC shows a close to 0.1 factor between layers and density, and TLC around 0.13, notably better than the 0.06-ish from the competing non-SGVC 3D NAND.
Based on the Switch cartridge's dimension of 21 mm x 31 mm and
this image, it appears that the current Macronix chip package is around 18 mm x 14.5 mm (261 mm²), and the memory die itself is around 14 mm x 9.5 mm (133 mm²). The Breath of the Wild cartridge pictured here has 16 GB capacity, so the memory density of the die in this MX23K128GL0 is around 0.96 Gb/mm². Note that this and other density estimates are not accounting for the peripherals/connectors and assuming everything is die size-only, which may not be the case for other figures (which I believe would lead to slightly conservative estimates of density/capacity in my comparisons, not overestimations).
I don't know anything about the defect rate, die size limitations, etc. in 3D NAND processes, but we can assume that something around the size of the Switch game card memory is doable (despite the fact that all the dies listed in the TechInsights article are only between 46.5 and 73.6 mm²). I say this mostly because in the SGVC paper, Macronix claimed 48 TLC layers could provide around 6.2 Gb/mm² density and deliver a 1 Tb single-chip solution, which implies a die area of about 165 mm², which is larger than the BotW cartridge die, but still within the package area of 261 mm² and well within the total cartridge area of 651 mm². So we can assume such a die area is feasible from a manufacturing perspective.
Turning back to the regular 3D NAND from Macronix, let's assume the same 133 mm² die size as BotW and take the extrapolated density numbers from the above (bearing in mind the amount of napkin math that went into this). That would coincidentally give us capacities of 48 GB for 48 layers, 96 GB for 96 layers, and 192 GB for 192 layers. In short, if the scaling is close enough to linear, and Macronix's density is about as good as the competitions, then Switch 2 cartridge sizes up to 96 GB should be covered by the 3D NAND Macronix is already mass producing, and sizes up to 192 GB would be covered by the 192-layer chips which were supposed to enter mass production sometime this year.
Note that I'm not saying we'll see this exact correspondence between layer count and capacity in practice. For one thing, 128 GB is probably the maximum capacity we'll ever see, and obviously it saves money to manufacture capacities only as large as needed. Moreover, to account for the roughness of the estimate, we can assume that the die size can be increased or decreased to an extent to achieve desired capacities.
On the other hand, if SGVC NAND were used, BotW's die size would yield capacities approximately like this:
Layers | MLC Capacity (GB) | TLC Capacity (GB) |
---|
16 | 26 | 40 |
24 | 40 | 54 |
32 | 50 | 70 |
48 | 76 | 103 |
At the time the SGVC paper was published in 2017, 48 layers was probably considered a lot, but with current chips using 128-176 and as high as 232 layers, scaling this up to capacities of 128 GB should be perfectly doable. The die size could also be increased from the 133 mm² assumption I'm making here. As a reminder, SGVC NAND is said to be cheaper and (importantly for Nintendo) long-lasting and wear-resistant without the need for self-refreshing. The only things that ought to stop Nintendo from using it would be the tech not panning out, or not being available in time.
One thing to note here is that the lower layer counts are only relevant if manufacturing isn't available for higher layer chips. The more layers, the cheaper the chip is per bit! If 192-layer chips are available, or whatever the maximum is for SGVC, it would be the most cost-effective to manufacture every capacity with that many layers, and simply adjust the die area to achieve the desired capacity.